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Introduction to the C2H Compiler
System Architecture
Figure 1–1 shows the architecture of a simple Nios II processor system
that includes one hardware accelerator.
Figure 1–1. Example System Topology with Single Hardware Accelerator
S
Nios II
Processor
Control
Hardware
Avalon
Switch
Fabric
Instruction
M
Data
M
MUX
Arbitrator
Accelerator
M
M
Arbitrator
S
Instruction
Memory
S
Peripherals
S
Data
Memory
S
Data
Memory
Write Data & Control Path
Read Data
M
S
Avalon Master Port
Avalon Slave Port
SOPC Builder automatically integrates the accelerator logic into the
system as an SOPC Builder component. If there is more than one
accelerator in the system, multiple accelerators appear in SOPC Builder.
Accelerators are separate from the Nios II processor but can access the
same memory devices that the Nios II processor can.
Altera Corporation
November 2009
9.1
1–9
Nios II C2H Compiler User Guide
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